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VLSI Physical Design_ From Graph Partitioning to Timing Closure

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VLSI Physical Design_ From Graph Partitioning to Timing Closure

by
Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu

Topics
routing, net, nets, placement, design, algorithm, timing, global, node, cell, global routing, clock tree, detailed placement, physical design, detailed routing, timing closure, chip planning, global placement, spanning tree, channel routing
Collection
folkscanomy_electronics; folkscanomy; additional_collections
Language
English
VLSI Physical Design_ From Graph Partitioning to Timing Closure
Identifier
VLSI_Physical_Design_From_Graph_Partitioning_to_Timing_Closure
Identifier-ark
ark:/13960/t2z33fz9g
Ocr
ABBYY FineReader 8.0
Pages
319
Ppi
300

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